🎛️ Input Controls
Input A
Input B
Input Cin
⚡ Full Adder Logic Circuit (2 Half Adders + 1 OR Gate)
📊 Output State & Intermediate Signals
Primary Outputs
SUM
0
CARRY OUT (COUT)
0
Internal Stage Signals
Partial Sum (HA1 XOR)
0
Carry 1 (HA1 AND)
0
Carry 2 (HA2 AND)
0
Boolean Expressions
Partial Sum = A ⊕ BCarry 1 = A · BSUM = Partial Sum ⊕ Cin = A ⊕ B ⊕ CinCarry 2 = Partial Sum · CinCOUT = Carry 1 + Carry 2 = (A·B) + ((A⊕B)·Cin)
📋 Full Adder Truth Table (3 Inputs → 8 States)
| A | B | Cin | SUM (S) | COUT | Active Row |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | |
| 0 | 0 | 1 | 1 | 0 | |
| 0 | 1 | 0 | 1 | 0 | |
| 0 | 1 | 1 | 0 | 1 | |
| 1 | 0 | 0 | 1 | 0 | |
| 1 | 0 | 1 | 0 | 1 | |
| 1 | 1 | 0 | 0 | 1 | |
| 1 | 1 | 1 | 1 | 1 |
📖 Theory & Working Principle
What is a Full Adder?
A Full Adder is a combinational digital circuit that performs arithmetic addition of three single-bit binary numbers: two main data inputs (A and B) and an incoming carry bit (Cin) from a previous less-significant bit position.
Key Difference Between SUM and CARRY OUT
- SUM (S): Represents the least significant bit (LSB) of the 3-input binary sum result (0 + 0 + 0 = 0, 1 + 0 + 0 = 1, 1 + 1 + 0 = 0 with carry, 1 + 1 + 1 = 1 with carry).
- CARRY OUT (COUT): Represents the most significant bit (MSB) carry bit generated whenever two or more inputs are logic 1 (high).
Cascaded Construction: 2 Half Adders + 1 OR Gate
A Full Adder can be cleanly constructed by cascading two Half Adder modules and combining their carry signals with an OR gate:
1. Half Adder 1 (HA1)
Processes original inputs A and B.
- Partial Sum:
A ⊕ B(fed into HA2) - Carry 1:
A · B(fed into OR gate)
2. Half Adder 2 (HA2)
Processes Partial Sum and incoming carry Cin.
- SUM:
Partial Sum ⊕ Cin = A ⊕ B ⊕ Cin - Carry 2:
Partial Sum · Cin(fed into OR gate)
3. OR Gate Stage
Combines the two potential carry paths (Carry 1 OR Carry 2).
- COUT:
Carry 1 + Carry 2 = (A·B) + ((A⊕B)·Cin)